View LTC1415_296058.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

LTC1415 12-Bit, 1.25Msps, 55mW Sampling A/D Converter
FEATURES
s s s s s s s s s s
DESCRIPTIO
1.25Msps Sample Rate Single 5V Supply Power Dissipation: 55mW Nap and Sleep Power Shutdown Modes 0.35LSB INL and 0.25LSB DNL 72dB S/(N + D) and 80dB THD at 100kHz External or Internal Reference Operation True Differential Inputs Reject Common Mode Noise Input Range: 4.096V (1mV/LSB) 28-Pin SSOP and SO Packages
The LTC (R)1415 is a 700ns, 1.25Msps, 12-bit sampling A/D converter that draws only 55mW from a single 5V supply. This easy-to-use device includes a high dynamic range sample-and-hold, precision reference and a trimmed internal clock. Two power shutdown modes provide flexibility for low power systems. The LTC1415's full-scale input range is 4.096V. Low linearity errors 0.35LSB INL, 0.25LSB DNL make it ideal for imaging systems. Outstanding AC performance includes 72dB S/(N + D) and 80dB THD with an input frequency of 100kHz. The unique differential input sample-and-hold can acquire single-ended or differential input signals up to its 18MHz bandwidth. The 60dB common mode rejection allows users to eliminate ground loops and common mode noise by measuring signals differentially from the source. The ADC has a P compatible, 12-bit parallel output port. There is no pipeline delay in the conversion results. A separate convert start input and data ready signal (BUSY) ease connections to FIFOs, DSPs and microprocessors. A separate output logic supply pin allows direct connection to 3V components.
APPLICATI
s s s s s
S
High Speed Data Acquisition Imaging Systems Digital Signal Processing Multiplexed Data Acquisition Systems Telecommunications
, LTC and LT are registered trademarks of Linear Technology Corporation.
TYPICAL APPLICATI
LTC1415 DIFFERENTIAL 1 +AIN ANALOG INPUT (0V TO 4.096V) 2 -AIN 2.50V 3 V VREF OUTPUT 4 REF REFCOMP 5 AGND 10F 6 D11(MSB) 7 D10 8 D9 9 D8 10 D7 11 12-BIT D6 PARALLEL 12 D5 BUS 13 D4 14 DGND
1.25MHz, 12-Bit Sampling A/D Converter
5V AVDD DVDD OVDD BUSY CS CONVST RD SHDN NAP/SLP OGND D0 D1 D2 D3 28 27 26 25 24 23 22 21 20 19 18 17 16 15 P CONTROL LINES OUTPUT LOGIC SUPPLY 3V OR 5V 10F
Effective Bits and Signal-to-(Noise + Distortion) vs Input Frequency
12 11 10 9 NYQUIST FREQUENCY 74 68 62 56
EFFECTIVE BITS
8 7 6 5 4 3 2 1 0 1k 10k 100k INPUT FREQUENCY (Hz) 1M 2M fSAMPLE = 1.25Msps
1415 TA01
U
SIGNAL/(NOISE + DISTORTION) (dB)
LTC1415 * TA02
UO
UO
1
LTC1415 ABSOLUTE AXI U RATI GS
PACKAGE/ORDER I FOR ATIO
TOP VIEW +AIN 1 -AIN 2 VREF 3 REFCOMP 4 AGND 5 D11 (MSB) 6 D10 7 D9 8 D8 9 D7 10 D6 11 D5 12 D4 13 DGND 14 G PACKAGE 28-LEAD PLASTIC SSOP 28 AVDD 27 DVDD 26 OVDD 25 BUSY 24 CS 23 CONVST 22 RD 21 SHDN 20 NAP/SLP 19 OGND 18 D0 17 D1 16 D2 15 D3 SW PACKAGE 28-LEAD PLASTIC SO WIDE
AVDD = DVDD =OVDD = VDD (Notes 1, 2)
Supply Voltage (VDD) ................................................ 6V Analog Input Voltage (Note 3) ...... - 0.3V to VDD + 0.3V Digital Input Voltage (Note 4) .................. - 0.3V to 12V Digital Output Voltage .................... - 0.3V to VDD + 0.3V Power Dissipation............................................. 500mW Operating Temperature Range LTC1415C............................................... 0C to 70C LTC1415I........................................... - 40C to 85C Storage Temperature Range ................ - 65C to 150C Lead Temperature (Soldering, 10 sec)................. 300C
ORDER PART NUMBER LTC1415CG LTC1415CSW LTC1415IG LTC1415ISW
TJMAX = 110C, JA = 95C/W (G) TJMAX = 110C, JA = 130C/W (SW)
Consult factory for Military grade parts.
CO VERTER CHARACTERISTICS
PARAMETER Resolution (No Missing Codes) Integral Linearity Error Differential Linearity Error Offset Error Full-Scale Error Full-Scale Tempco
With Internal Reference (Notes 5, 6)
MIN
q
CONDITIONS (Note 7) (Note 8)
q q q
TYP 0.35 0.25 1
MAX 1 1 6 8 20
UNITS Bits LSB LSB LSB LSB LSB ppm/C
12
IOUT(REF) = 0
15
A ALOG I PUT
SYMBOL PARAMETER VIN IIN CIN t ACQ t AP tjitter CMRR
(Note 5)
CONDITIONS 4.75V VDD 5.25V CS = High Between Conversions During Conversions
q q q
MIN
TYP 4.096
MAX 1
UNITS V A pF pF
Analog Input Range (Note 9) Analog Input Leakage Current Analog Input Capacitance Sample-and-Hold Acquisition Time Sample-and-Hold Aperture Delay Time Sample-and-Hold Aperture Delay Time Jitter Analog Input Common Mode Rejection Ratio
19 5 50 -1.5 2 150
psRMS dB
0V < VCM < VDD, DC to MHz
60
2
U
ns ns
W
U
U
WW
W
U
U
U
LTC1415
DY A IC ACCURACY
SYMBOL S/(N + D) THD SFDR IMD PARAMETER
I TER AL REFERE CE CHARACTERISTICS
PARAMETER VREF Output Voltage VREF Output Tempco VREF Line Regulation VREF Output Resistance REFCOMP Output Voltage CONDITIONS IOUT = 0 IOUT = 0 4.75V VDD 5.25V
IOUT 0.1mA
DIGITAL I PUTS A D DIGITAL OUTPUTS
SYMBOL PARAMETER VIH VIL IIN CIN VOH High Level Input Voltage Low Level Input Voltage Digital Input Current Digital Input Capacitance High Level Output Voltage VDD = 4.75V IO = - 10A IO = - 200A VDD = 4.75V IO = 160A IO = 1.6mA VOUT = 0V to VDD, CS High CS High (Note 9 ) VOUT = 0V VOUT = VDD CONDITIONS VDD = 5.25V VDD = 4.75V VIN = 0V to VDD
VOL
Low Level Output Voltage
IOZ COZ ISOURCE ISINK
Hi-Z Output Leakage D11 to D0 Hi-Z Output Capacitance D11 to D0 Output Source Current Output Sink Current
POWER REQUIRE E TS
SYMBOL PARAMETER VDD IDD Supply Voltage Supply Current Nap Mode Sleep Mode Power Dissipation Nap Mode Sleep Mode
PD
UW
U
U
U
WU
U
(Note 5)
CONDITIONS 100kHz Input Signal 600kHz Input Signal 100kHz Input Signal, First 5 Harmonics 600kHz Input Signal, First 5 Harmonics 600kHz Input Signal fIN1 = 29.37kHz, fIN2 = 32.446kHz S/(N + D) 68dB MIN TYP 72 69 - 80 - 72 - 75 - 84 18 1 MAX UNITS dB dB dB dB dB dB MHz MHz
Signal-to-(Noise + Distortion) Ratio Total Harmonic Distortion Spurious Free Dynamic Range Intermodulation Distortion Full-Power Bandwidth Full-Linear Bandwidth
U
(Note 5)
MIN 2.480 TYP 2.500 15 0.01 2 4.096 MAX 2.520 UNITS V ppm/C LSB/V k V
IOUT = 0
(Note 5)
MIN
q q q
TYP
MAX 0.8 10
UNITS V V A pF V V V V A pF mA mA
2.4
5 4.5
q
4.0 0.05 0.10
q q q
0.4 10 15
- 10 10
(Note 5)
CONDITIONS (Notes 10, 11) CS High SHDN = 0V, NAP/SLP = 5V (Note 12) SHDN = 0V, NAP/SLP = 0V (Note 12) CS High SHDN = 0V, NAP/SLP = 5V SHDN = 0V, NAP/SLP = 0V
q q
MIN 4.75
TYP 11 1.5 1.0 55 7.5 0.01
MAX 5.25 20 2.3 100 12
UNITS V mA mA A mW mW mW
3
LTC1415
TI I G CHARACTERISTICS
SYMBOL fSAMPLE(MAX) tCONV tACQ t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 PARAMETER Maximum Sampling Frequency Conversion and Acquisition Time Conversion Time Acquisition Time CS to RD Setup Time CS to CONVST Setup Time NAP/SLP to SHDN Setup Time
t11
t12 t13 t14
The q denotes specifications which apply over the full operating temperature range; all other limits and typicals TA = 25C. Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: All voltage values are with respect to ground with DGND and AGND wired together unless otherwise noted. Note 3: When these pin voltages are taken below ground or above VDD, they will be clamped by internal diodes. This product can handle input currents greater than 100mA below ground or above VDD without latchup. Note 4: When these pin voltages are taken below ground, they will be clamped by internal diodes. This product can handle input currents greater than 100mA below ground without latchup. These pins are not clamped to VDD. Note 5: VDD = 5V, fSAMPLE = 1.25MHz, tr = tf = 5ns unless otherwise specified.
4
UW
(Note 5)
MIN
q q q q
CONDITIONS
TYP
MAX 800 700 150
UNITS MHz ns ns ns ns ns
1.25
(Notes 9, 10) (Notes 9, 10) (Notes 9, 10)
q q
0 10 200 200 10
ns ns ms ns ns ns ns ns ns ns
SHDN to CONVST Wake-Up Time Nap Mode (Note 10) Sleep Mode, CREFCOMP = 10F (Note 10) CONVST Low Time CONVST to BUSY Delay Data Ready Before BUSY
q
(Notes 10, 11) CL = 25pF
q q
50 10 60 20 15 50 -5 20 35 45 45 60 30 35 40 35
Delay Between Conversions Wait Time RD After BUSY Data Access Time After RD
(Note 10) CL = 25pF
q q q
ns ns ns ns ns ns ns ns ns
CL = 100pF
q
25 10
Bus Relinquish Time 0C = TA = 70C - 40C = TA = 85C RD Low Time CONVST High Time Aperture Delay of Sample-and-Hold
q q q q
t 10 50 - 1.5
ns
Note 6: Linearity, offset and full-scale specifications apply for a singleended +AIN input with - AIN grounded. Note 7: Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band. Note 8: Bipolar offset is the offset voltage measured from - 0.5LSB when the output code flickers between 0000 0000 0000 and 1111 1111 1111. Note 9: Guaranteed by design, not subject to test. Note 10: Recommended operating conditions. Note 11: The falling edge of CONVST starts a conversion. If CONVST returns high at a critical point during the conversion it can create small errors. For best performance ensure that CONVST returns high either within 425ns after the start of the conversion or after BUSY rises. Note 12: CS = RD = CONVST = 0V.
LTC1415 TYPICAL PERFORMANCE CHARACTERISTICS
S/(N + D) vs Input Frequency and Amplitude
80 VIN = 0dB
SIGNAL/(NOISE + DISTORTION) (dB)
AMPLITUDE (dB BELOW THE FUNDAMENTAL)
70
SIGNAL-TO -NOISE RATIO (dB)
60 50 40 30 20 10 0 1k
VIN = -20dB
VIN = -60dB
10k 100k INPUT FREQUENCY (Hz)
Spurious-Free Dynamic Range vs Input Frequency
0 0 -20 -20 -30 -40 -50 -60 -70 -80 -90 10k -120 100k INPUT FREQUENCY (Hz) 1M 2M
AMPLITUDE (dB)
SPURIOUS-FREE DYNAMIC RANGE (dB)
-10
Integral Nonlinearity vs Output Code
1.00 1.00
0.50
DNL ERROR (LSBs) INL ERROR (LSBs)
0.00
-0.50
-1.00 0 512 1024 1536 2048 2560 3072 3584 4096 OUTPUT CODE
LTC1415 * TPC07
UW
LTC1415 * TPC01 LTC1415 * TPC04
Signal-to-Noise Ratio vs Input Frequency
80 70 60 50 40 30 20 10 0 1M 2M 1k 10k 100k INPUT FREQUENCY (Hz) 1M 2M
LTC1415 * TPC02
Distortion vs Input Frequency
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 1k 10k 100k INPUT FREQUENCY (Hz) 1M 2M
LTC1415 * TPC03
THD 2ND 3RD
Intermodulation Distortion Plot
fSAMPLE = 1.25MHz fIN1 = 86.97509766kHz fIN2 = 113.2202148kHz
-40 fb - fa -60 2fa - fb -80 2fa 2fb - fa fa + fb 2fb 3fa 2fa + fb fa + 2fb 3fb
-100
0
100k
200k
300k FREQUENCY (Hz)
400k
500k
600k
LTC1415 * TPC05
Differential Nonlinearity vs Output Code
0.50
0.00
-0.50
-1.00 0 512 1024 1536 2048 2560 3072 3584 4096 OUTPUT CODE
LTC1415 * TPC06
5
LTC1415 TYPICAL PERFORMANCE CHARACTERISTICS
AMPLITUDE OF POWER SUPPLY FEEDTHROUGH (dB)
Power Supply Feedthrough vs Ripple Frequency
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 1k VDD DGND OVDD 100k 10k RIPPLE FREQUENCY (Hz) 1M 2M
COMMON MODE REJECTION (dB)
PI FU CTIO S
+ AIN (Pin 1): Positive Analog Input, 0V to 4.096V. - AIN (Pin 2): Negative Analog Input, 0V to 4.096V. VREF (Pin 3): 2.50V Reference Output. REFCOMP (Pin 4): Bypass to AGND with 10F tantalum in parallel with 0.1F or 10F ceramic. AGND (Pin 5): Analog Ground. D11 to D4 (Pins 6 to 13): Three-State Data Outputs. DGND (Pin 14): Digital Ground. D3 to D0 (Pins 15 to 18): Three-State Data Outputs. OGND (Pin 19): Digital Output Buffer Ground. NAP/SLP (Pin 20): Power Shutdown Mode. High for quick wake-up Nap mode. SHDN (Pin 21): Power Shutdown Input. A low logic level will invoke the Shutdown mode selected by the NAP/SLP pin. Tie high if unused. RD (Pin 22): Read Input. This enables the output drivers when CS is low. CONVST (Pin 23): Conversion Start Signal. This active low signal starts a conversion on its falling edge. CS (Pin 24): The Chip Select input must be low for the ADC to recognize CONVST and RD inputs. BUSY (Pin 25): The BUSY output shows the converter status. It is low when a conversion is in progress. Its rising edge may be used to latch the output data. 0VDD (Pin 26): Digital output buffer supply. Short to Pin 28 for 5V output. Tie to 3V for driving 3V logic. DVDD (Pin 27): 5V Positive Supply. Short to Pin 28. AVDD (Pin 28): 5V Positive Supply. Bypass to AGND with 10F tantalum in parallel with 0.1F or 10F ceramic.
6
UW
Input Common Mode Rejection vs Input Frequency
80 70 60 50 40 30 20 10 0 1k 10k 100k INPUT FREQUENCY (Hz) 1M 2M
LTC1415 * TPC09
LTC1415 * TPC08
U
U
U
LTC1415
FU CTIO AL BLOCK DIAGRA
+AIN CSAMPLE - AIN 2k VREF 2.5V REF ZEROING SWITCHES AVDD DVDD
REF AMP
REFCOMP (4.096V) AGND DGND INTERNAL CLOCK CONTROL LOGIC SUCCESSIVE APPROXIMATION REGISTER 12 OUTPUT LATCHES * * *
NAP/SLP SHDN CONVST RD CS
TEST CIRCUITS
Load Circuits for Access Timing
5V 1k DBN 1k CL DBN CL DBN 1k 100pF DBN 100pF
(A) Hi-Z TO VOH AND VOL TO VOH
(B) Hi-Z TO VOL AND VOH TO VOL
1415 TC01
W
CSAMPLE
U
U
+
12-BIT CAPACITIVE DAC COMP
-
OVDD D11 D0 OGND
BUSY
1415 BD
Load Circuits for Bus Relinquish Time
5V 1k
(A) VOH TO Hi-Z
(B) VOL TO Hi-Z
1415 TC02
7
LTC1415
APPLICATIONS INFORMATION
CONVERSION DETAILS The LTC1415 uses a successive approximation algorithm and an internal sample-and-hold circuit to convert an analog signal to a 12-bit parallel output. The ADC is complete with a precision reference and an internal clock. The control logic provides easy interface to microprocessors and DSPs (please refer to Digital Interface section for the data format). Conversion start is controlled by the CS and CONVST inputs. At the start of the conversion the successive approximation register (SAR) is reset. Once a conversion cycle has begun it cannot be restarted. During the conversion, the internal differential 12-bit capacitive DAC output is sequenced by the SAR from the most significant bit (MSB) to the least significant bit (LSB). Referring to Figure 1, the +AIN and -AIN inputs are connected to the sample-and-hold capacitors (CSAMPLE) during the acquire phase and the comparator offset is nulled by the zeroing switches. In this acquire phase, a minimum delay of 150ns will provide enough time for the sampleand-hold capacitors to acquire the analog signal. During the convert phase the comparator zeroing switches open, putting the comparator into compare mode. The input switches the connect CSAMPLE capacitors to ground, transferring the differential analog input charge onto the summing junction. This input charge is successively compared
+CSAMPLE +AIN SAMPLE HOLD SAMPLE -CSAMPLE HOLD +CDAC ZEROING SWITCHES HOLD
AMPLITUDE (dB)
-AIN
HOLD
+
+VDAC -CDAC COMP
-
12 SAR
-VDAC
OUTPUT LATCHES
LTC1415 * F01
Figure 1. Simplified Block Diagram
8
U
W
U
U
with the binary weighted charges supplied by the differential capacitive DAC. Bit decisions are made by the high speed comparator. At the end of a conversion, the differential DAC output balances the + AIN and - AIN input charges. The SAR contents (a 12-bit data word) which represents the difference of + AIN and - AIN are loaded into the 12-bit output latches. DYNAMIC PERFORMANCE The LTC1415 has excellent high speed sampling capability. FFT (Fast Fourier Transform) test techniques are used to test the ADC's frequency response, distortion and noise at the rated throughput. By applying a low distortion sine wave and analyzing the digital output using a FFT algorithm, the ADC's spectral content can be examined for frequencies outside the fundamental. Figure 2 shows a typical LTC1415 FFT plot.
0 -20 -40 -60 -80 -100 -120 0 100 200 300 400 FREQUENCY (kHz) 500 600 fSAMPLE = 1.25MHz fIN = 99.792kHz SFDR - 87.5 SINAD = 72.1
LTC1415 * F02
Figure 2. LTC1415 Nonaveraged, 4096 Point FFT
Signal-to-Noise Ratio The signal-to-noise plus distortion ratio [S/(N + D)] or SINAD is the ratio between the RMS amplitude of the fundamental input frequency to the RMS amplitude of all other frequency components at the A/D output. The output is band limited to frequencies from above DC and below half the sampling frequency. Figure 2 shows a typical spectral content with a 1.25MHz sampling rate and a 100kHz input. The dynamic performance is excellent for input frequencies up to the Nyquist limit of 625kHz.
* D11 * * D0
LTC1415
APPLICATIONS INFORMATION
Effective Number of Bits The effective number of bits (ENOBs) is a measurement of the resolution of an ADC and is directly related to the S/(N + D) by the equation: N = [S/(N + D) - 1.76]/6.02 where N is the effective number of bits of resolution and S/(N + D) is expressed in dB. At the maximum sampling rate of 1.25MHz the LTC1415 maintains very good ENOBs up to the Nyquist input frequency of 625kHz (refer to Figure 3). Total Harmonic Distortion Total Harmonic Distortion (THD) is the ratio of the RMS sum of all harmonics of the input signal to the fundamental itself. The out-of-band harmonics alias into the frequency
12 11 10 9
EFFECTIVE BITS
68 62 56
AMPLITUDE (dB BELOW THE FUNDAMENTAL)
74
SIGNAL/(NOISE + DISTORTION) (dB)
8 7 6 5 4 3 2 1 0 1k 100k 10k INPUT FREQUENCY (Hz) 1M 2M
LT1415 * F03
Figure 3. Effective Bits and Signal/(Noise + Distortion) vs Input Frequency
0 -20
AMPLITUDE (dB)
-40 fb - fa -60 2fa - fb -80 2fa 2fb - fa fa + fb 2fb 3fa 2fa + fb fa + 2fb 3fb
-100 -120 0 100k 200k 300k FREQUENCY (Hz) 400k 500k 600k
LTC1415 * F05
Figure 5. Intermodulation Distortion Plot
U
W
U
U
band between DC and half the sampling frequency. THD is expressed as: V22 + V32 + V42 + ...Vn2 V1 where V1 is the RMS amplitude of the fundamental frequency and V2 through Vn are the amplitudes of the second through nth harmonics. THD vs input frequency is shown in Figure 4. The LTC1415 has good distortion performance up to the Nyquist frequency and beyond. THD = 20Log Intermodulation Distortion If the ADC input signal consists of more than one spectral component, the ADC transfer function nonlinearity can produce intermodulation distortion (IMD) in addition to THD. IMD is the change in one sinusoidal input caused by
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 1k 100k 10k INPUT FREQUENCY (Hz) 1M 2M
LTC1415 * F04
THD 2ND 3RD
Figure 4. Distortion vs Input Frequency
fSAMPLE = 1.25MHz fIN1 = 86.97509766kHz fIN2 = 113.2202148kHz
9
LTC1415
APPLICATIONS INFORMATION
the presence of another sinusoidal input at a different frequency. If two pure sine waves of frequencies fa and fb are applied to the ADC input, nonlinearities in the ADC transfer function can create distortion products at the sum and difference frequencies of mfa + - nfb, where m and n = 0, 1, 2, 3, etc. For example, the 2nd order IMD terms include (fa + fb). If the two input sine waves are equal in magnitude, the value (in decibels) of the 2nd order IMD products can be expressed by the following formula: only a small leakage current. If the source impedance of the driving circuit is low, then the LTC1415 inputs can be driven directly. As source impedance increases so will acquisition time (see Figure 6). For minimum acquisition time with high source impedance, a buffer amplifier should be used. The only requirement is that the amplifier driving the analog input(s) must settle after the small current spike before the next conversion starts (settling time must be 150ns for full throughput rate).
10
ACQUISITION TIME (s)
IMD( fa + fb) = 20Log
Amplitude at (fa + fb) Amplitude at fa
Peak Harmonic or Spurious Noise The peak harmonic or spurious noise is the largest spectral component excluding the input signal and DC. This value is expressed in decibels relative to the RMS value of a full-scale input signal. Full-Power and Full-Linear Bandwidth The full-power bandwidth is that input frequency at which the amplitude of the reconstructed fundamental is reduced by 3dB for a full-scale input signal. The full-linear bandwidth is the input frequency at which the S/(N + D) has dropped to 68dB (11 effective bits). The LTC1415 has been designed to optimize input bandwidth, allowing the ADC to undersample input signals with frequencies above the converter's Nyquist Frequency. The noise floor stays very low at high frequencies; S/(N + D) becomes dominated by distortion at frequencies far beyond Nyquist. Driving the Analog Input The differential analog inputs of the LTC1415 are easy to drive. The inputs may be driven differentially or as a singleended input (i.e., the -AIN input is grounded). The +AIN and -AIN inputs are sampled at the same instant. Any unwanted signal that is common mode to both inputs will be reduced by the common mode rejection of the sample-and-hold circuit. The inputs draw only one small current spike while charging the sample-and-hold capacitors at the end of conversion. During conversion the analog inputs draw
10
U
W
U
U
1
0.1
0.01 0.01
1 10 0.1 SOURCE RESISTANCE (k)
100
1415 F06
Figure 6. Acquisition Time vs Source Resistance
Choosing an Input Amplifier Choosing an input amplifier is easy if a few requirements are taken into consideration. First, to limit the magnitude of the voltage spike seen by the amplifier from charging the sampling capacitor, choose an amplifier that has a low output impedance (< 100) at the closed-loop bandwidth frequency. For example, if an amplifier is used in a gain of +1 and has a unity-gain bandwidth of 50MHz, then the output impedance at 50MHz should be less than 100. The second requirement is that the closed-loop bandwidth must be greater than 20MHz to ensure adequate small-signal settling for full throughput rate. If slower op amps are used, more settling time can be provided by increasing the time between conversions. The best choice for an op amp to drive the LTC1415 will depend on the application. Generally applications fall into two categories: AC applications where dynamic specifications are most critical and time domain applications where DC accuracy and settling time are most critical.
LTC1415
APPLICATIONS INFORMATION
The following list is a summary of the op amps that are suitable for driving the LTC1415, more detailed information is available in the Linear Technology databooks and the LinearViewTM CD-ROM. LT (R) 1215/LT1216: Dual and quad 23MHz, 50V/s single supply op amps. Single 5V to 15V supplies, 6.6mA specifications, 90ns settling to 0.5LSB. LT1223: 100MHz video current feedback amplifier. 5V to 15V supplies, 6mA supply current. Low distortion up to and above 400kHz. Low noise. Good for AC applications. LT1227: 140MHz video current feedback amplifier. 5V to 15V supplies, 10mA supply current. Lowest distortion at frequencies above 400kHz. Low noise. Best for AC applications. LT1229/LT1230: Dual and quad 100MHz current feedback amplifiers. 2V to 15V supplies, 6mA supply current each amplifier. Low noise. Good AC specs. LT1360: 37MHz voltage feedback amplifier. 5V to 15V supplies. 3.8mA supply current. Good AC and DC specs. 70ns settling to 0.5LSB. LT1363: 50MHz, 450V/s op amps. 5V to 15V supplies. 6.3mA supply current. Good AC and DC specs. 60ns settling to 0.5LSB. LT1364/LT1365: Dual and quad 50MHz, 450V/s op amps. 5V to 15V supplies, 6.3mA supply current per amplifier. 60ns settling to 0.5LSB. Input Filtering The noise and the distortion of the input amplifier and other circuitry must be considered since they will add to the LTC1415 noise and distortion. The small-signal bandwidth of the sample-and-hold circuit is 20MHz. Any noise or distortion products that are present at the analog inputs will be summed over this entire bandwidth. Noisy input circuitry should be filtered prior to the analog inputs to minimize noise. A simple 1-pole RC filter is sufficient for many applications. For example Figure 7 shows a 1000pF capacitor from +AIN to ground and a 100 source resistor to limit the input bandwidth to 1.6MHz. The 1000pF
LinearView is a trademark of Linear Technology Corporation.
U
W
U
U
capacitor also acts as a charge reservoir for the input sample-and-hold and isolates the ADC input from sampling glitch sensitive circuitry. High quality capacitors and resistors should be used since these components can add distortion. NPO and silver mica type dielectric capacitors have excellent linearity. Carbon surface mount resistors can also generate distortion from self heating and from damage that may occur during soldering. Metal film surface mount resistors are much less susceptible to both problems.
100 1000pF 2 -AIN LTC1415 3 VREF 1
ANALOG INPUT
+AIN
4 10F 5
REFCOMP
AGND
LTC1415 * F07
Figure 7. RC Input Filter
Input Range The 4.096V input range of the LTC1415 is optimized for low noise. Most single supply op amps also perform well over this same range, allowing direct coupling to the analog inputs and eliminating the need for special translation circuitry. Some applications may require other input ranges. The LTC1415 differential inputs and reference circuitry can accommodate other input ranges often with little or no additional circuitry. The following sections describe the reference and input circuitry and how they affect the input range. Internal Reference The LTC1415 has an on-chip, temperature compensated, curvature corrected, bandgap reference that is factory trimmed to 2.500V. It is connected internally to a reference amplifier and is available at VREF (Pin 3) see Figure 8a. A 2k resistor is in series with the output so that it can be easily overdriven by an external reference or other
11
LTC1415
APPLICATIONS INFORMATION
circuitry. The reference amplifier gains the voltage at the VREF pin by 1.638 to create the required internal reference voltage of 4.096V. This provides buffering between the VREF pin and the high speed capacitive DAC. The reference amplifier compensation pin (REFCOMP, Pin 4) must be bypassed with a capacitor to ground. The reference amplifier is stable with capacitors of 1F or greater. For the best noise performance a 10F ceramic or tantalum in parallel with a 0.1F ceramic is recommended.
R1 2k
1 DIFFERENTIAL ANALOG INPUT RANGE = (VREF)(1.638) +AIN 2 -AIN LTC1415 1.25V TO 3V 3 VREF
V 2.500V 3 REF
BANDGAP REFERENCE
4.096V
4 REFCOMP
REFERENCE AMP R2 40k
10F R3 64k
5 AGND
LTC1415
LTC1415 * F08a
Figure 8a. LTC1415 Reference Circuit
5V VIN LT1019A-2.5 VOUT ANALOG INPUT 1 2 3
+AIN -AIN VREF
LTC1415
4 10F 5
REFCOMP
AGND
1415 F08b
Figure 8b. Using the LT1019-2.5 as an External Reference
The VREF pin can be driven with a DAC or other means shown in Figure 9. This is useful in applications where the peak input signal amplitude may vary. The input span of the ADC can then be adjusted to match the peak input signal, maximizing the signal-to-noise ratio. The filtering of the internal LTC1415 reference amplifier will limit the
12
U
W
U
U
LTC1450 12-BIT RAIL-TO-RAIL DAC
4 10F 5
REFCOMP
AGND
LTC1415 * F09
Figure 9. Driving VREF with a DAC to Adjust Full Scale
bandwidth and settling time of this circuit. A settling time of 5ms should be allowed for after a reference adjustment. Differential Inputs The LTC1415 has a unique differential sample-and-hold circuit that allows rail-to-rail inputs. The ADC will always convert the difference of +AIN - (-AIN) independent of the common mode voltage. The common mode rejection is constant from DC to 1MHz, see Figure 10a. The only requirement is that both inputs can not exceed the AVDD or AGND power supply voltages. Integral nonlinearity errors (INL) and differential nonlinearity errors (DNL) are independent of the common mode voltage, however, the bipolar zero error (BZE) will vary. The change in BZE is typically less than 0.1% of the common mode voltage. Differential inputs allow greater flexibility for accepting different input ranges. Figure 10b shows a circuit that shifts the input range up in voltage by 200mV. This can be useful in applications where the amplifier driving the ADC input is not able to swing all the way to ground, because of output loading or settling time issues. Some AC applications may have their performance limited by distortion. Most circuits exhibit higher distortion when signals approach the supply or ground. Distortion can be reduced by reducing the signal amplitude and keeping the common mode voltage at approximately midsupply. The circuit of Figure 10c reduces the ADC full scale from
LTC1415
APPLICATIONS INFORMATION
4.096V to 2.048V and shifts the common mode voltage from half of full scale to 2.274V. AC Coupled Inputs The analog inputs can be AC coupled for applications where the input has no DC information. The input of the
80
SIGNAL/(NOISE + DISTORTION) (dB)
70 60 50 40 30
20 10 0 1k 10k 100k INPUT FREQUENCY (Hz) 1M 2M
LTC1415 * F10a
Figure 10a. CMRR vs Input Frequency
ANALOG INPUT 1 +AIN 1.25V TO 3.298V 2 -AIN 24 3 VOUT = 1.2V VREF LT1004-1.2 1F LTC1415
4 10F 5
REFCOMP
AGND
LTC1415 * F10c
Figure 10c. 2.048V Input Range with a Common Mode Voltage of 2.274V. For Low Distortion AC Applications
ANALOG INPUT 2.048VP-P 25 1k LT1004-1.2 1 2 3 1F +AIN -AIN VREF
+ -
1k 9k
Figure 10e. 2.048VP-P Input Range with AC Coupling. For Low Distortion AC Applications
U
W
U
U
ADC does need to be DC biased at midscale. Figures 10d and 10e demonstrate AC coupling and the required biasing. Figure 10d shows the ADC with a full scale of 4.096V, a common mode voltage of 2.048V and an input that swings from 0V to 4.096V. This circuit has the lowest noise (SINAD = 72dB to 100kHz) but will have distortion
ANALOG INPUT 1 0.2V TO 4.296V R1 200 2 R2 3.9k 3 +AIN
-AIN LTC1415 VREF
4 10F 5
REFCOMP
AGND
LTC1415 * F10b
Figure 10b. Shifting the Input Range Up from Ground by 200mV
ANALOG INPUT 4.096VP-P 1 2 3 4 2k 10F 2k 5 AGND
LTC1415 * F10d
+AIN -AIN VREF LTC1415 REFCOMP
Figure 10d. 4.096VP-P Input Range with AC Coupling. For Low Noise AC Applications
LTC1415 4 REFCOMP
10F 5
AGND
LTC1415 * F10e
13
LTC1415
APPLICATIONS INFORMATION
limitations at high input frequencies (THD = 75dB at 600kHz). The ADC in Figure 10e has a full scale of 2.048V and a common mode of 2.27V. The reduced signal swing of this circuit results in improved distortion at higher input frequencies (THD = 82dB at 600kHz) but with worse SINAD at low frequencies (SINAD = 70dB at 100kHz). Full-Scale and Offset Adjustment Figure 11a shows the ideal input/output characteristics for the LTC1415. The code transitions occur midway between successive integer LSB values (i.e., 0.5LSB, 1.5LSB, 2.5LSB,... FS - 1.5LSB, FS - 0.5LSB). The output is straight binary with 1LSB = FS/4096 = 4.096V/4096 = 1mV.
10F ANALOG INPUT 5V R8 50k R5 47k R7 50k R6 24k 0.1F R1 100 R2 47k
111...111 111...110 111...101
OUTPUT CODE
000...010 000...001 000...000 1LSB INPUT VOLTAGE (V) FS - 1LSB
LTC1415 * F11a
Figure 11a. LTC1415 Transfer Characteristics
In applications where absolute accuracy is important, offset and full-scale errors can be adjusted to zero. Offset error must be adjusted before full-scale error. Figure 11b shows the extra components required for full-scale error adjustment. Zero offset is achieved by adjusting the offset applied to the - AIN input. For zero offset error apply 0.5mV (i.e., 0.5LSB) at +AIN and adjust the offset at the - AIN input (R8) until the output code flickers between 0000 0000 0000 and 0000 0000 0001. For full-scale adjustment, an input voltage of 4.0945V (FS - 1.5LSBs) is applied to the analog input and R7 is adjusted until
14
U
W
U
U
R3 24k R4 100
1 2 3
+AIN -AIN VREF
LTC1415
4
REFCOMP
5 AGND
LTC1415 * F11b
Figure 11b. Offset and Full-Scale Adjust Circuit
the output code flickers between 1111 1111 1110 and 1111 1111 1111. BOARD LAYOUT AND GROUNDING Wire wrap boards are not recommended for high resolution or high speed A/D converters. To obtain the best performance from the LTC1415, a printed circuit board with ground plane is required. The ground plane under the ADC area should be as free of breaks and holes as possible, such that a low impedance path between all ADC grounds and all ADC decoupling capacitors is provided. It is critical to prevent digital noise from being coupled to the analog input, reference or analog power supply lines. Layout should ensure that digital and analog signal lines are separated as much as possible. Particular care should be taken not to run any digital track alongside an analog signal track. An analog ground plane separate from the logic system ground should be established under and around the ADC. Pin 5 (AGND), Pin 14 and Pin 19 (ADC's DGND) and all other analog grounds should be connected to this single analog ground point. The REFCOMP bypass capacitor and the DVDD bypass capacitor should also be connected to this analog ground plane. No other digital grounds should be connected to this analog ground plane. Low impedance analog and digital power supply common returns are essential to low noise operation of the ADC and the foil
LTC1415
APPLICATIONS INFORMATION
width for these tracks should be as wide as possible. In applications where the ADC data outputs and control signals are connected to a continuously active microprocessor bus, it is possible to get errors in the conversion results. These errors are due to feedthrough from the microprocessor to the successive approximation comparator. The problem can be eliminated by forcing the microprocessor into a WAIT state during conversion or by using three-state buffers to isolate the ADC data bus. The traces connecting the pins and bypass capacitors must be kept short and should be made as wide as possible. The LTC1415 has differential inputs to minimize noise coupling. Common mode noise on the + AIN and - AIN leads will be rejected by the input CMRR. The - AIN input can be used as a ground sense for the + AIN input; the LTC1415 will hold and convert the difference voltage between + AIN and - AIN. The leads to + AIN (Pin 1) and - AIN (Pin 2) should be kept as short as possible. In applications where this is not possible, the + AIN and - AIN traces should be run side by side to equalize coupling. SUPPLY BYPASSING High quality, low series resistance ceramic, 10F bypass capacitors should be used at the VDD and REFCOMP pins as shown in the Typical Application on the fist page of this data sheet. Surface mount ceramic capacitors such as Murata GRM235Y5V106Z016 provide excellent bypassing in a small board space. Alternatively 10F tantalum capacitors in parallel with 0.1F ceramic capacitors can be used. Bypass capacitors must be located as close to the pins as possible. The traces connecting the pins and the bypass capacitors must be kept short and should be made as wide as possible. Example Layout Figures 13a, 13b, 13c and 13d show the schematic and layout of a suggested evaluation board. The layout demonstrates the proper use of decoupling capacitors and ground plane with a two layer printed circuit board.
1 ANALOG INPUT CIRCUITRY
+AIN -AIN REFCOMP AGND 2 4 10F 0.1F 5
+ -+
Figure 12. Power Supply Grounding Practice
U
W
U
U
LTC1415 AVDD 28 DVDD 27 0.1F OVDD DGND OGND 26 14 19
DIGITAL SYSTEM
LTC1415 * F12
+
10F ANALOG GROUND PLANE
15
3.3V
J1 GND U3 74HC574
R0 TO R11 1.2k D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10
J3 + AIN R15 51 C3 1000pF
B0 TO B11
R19 10k C4 1000pF U2 LTC1415 1 2 3 4 COMP BUSY CS CONVST RD SHDN AVDD DVDD OVDD AGND DGND NAP/SLP 20 11 OGND 19 D11 10 D0 18 B0 D1 17 B1 D2 16 B2 D3 15 B3 D4 13 B4 D5 12 B5 D6 11 B6 D7 10 B7 D8 9 B8 25 24 23 22 21 28 27 26 VCC 14 C6 10F 16V C2 10F 16V R14 1k 5 OVDD 14 U5C HC14 6 C13 15pF OVDD 5 VREF D9 8 B9 - AIN D10 7 B10 +AIN U4 74HC574 D11 6 B11
B0 B1 B2 B3 B11 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 19 18 17 16 15 14 13 12
D0 D1 D2 D3 D11
C8 1000pF
APPLICATIONS INFORMATION
R20 10k R16 51
JP3
D11 JP1 LED J6 HEADER
J5 - AIN
C5 1F 16V
C10 10F 16V
J7 CLK
U5A HC14
U5B HC14
1
23
4
B10 B9 B8 B7 B6 B5 B4
1 11 2 3 4 5 6 7 8 9 OE CLK D0 D1 D2 D3 D4 D5 D6 D7 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
19 18 17 16 15 14 13 12
D10 D9 D8 D7 D6 D5 D4
R13 51
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11
VCC
JP4D
CS
JP4C
RD
U5E HC14 9 U5D HC14 8
D11 RDY DGND DGND
JP4B
SHDN
11 12 9 10 7 8 5 6 3 4 1 2 13 14 15 16
JP4A R17 1M R18 1M
NAP/SLP
LTC1415 * F13a
U5F HC14 13 12
NOTES: UNLESS OTHERWISE SPECIFIED 1. ALL RESISTOR VALUE IN OHMS, 1/10W, 5% 2. ALL CAPACITOR VALUES IN F, 25V, 20% AND IN pF, 50V, 10%
C12 0.1F
VCC U5G HC14 GND 7
Figure 13a. Suggested Evaluation Circuit Schematic
U
1 11 2 3 4 5 6 7 8 9 OE CLK D0 D1 D2 D3 D4 D5 D6 D7
W
U
AGND DGND
U
16
VCC JP2A VCC 3.3V OVDD
J4 OPTIONAL
U1 LT1121-5
1
J2 7V TO 15V
VIN
VOUT
3
+
C1 22F 10V JP2B D0 TO D11 R12 20 C9 0.1F C11 0.1F
LTC1415
+
C7 10F 10V
GND 2
TAB 4
D15 SS12
LTC1415
APPLICATIONS INFORMATION U W U U
Figure 13b. Suggested Evaluation Circuit Board Component Side Silkscreen
Figure 13c. Suggested Evaluation Circuit Board Component Side Layout
17
LTC1415
APPLICATIONS INFORMATION U W U U
Figure 13d. Suggested Evaluation Circuit Board Solder Side Layout
DIGITAL INTERFACE The A/D converter is designed to interface with microprocessors as a memory mapped device. The CS and RD control inputs are common to all peripheral memory interfacing. A separate CONVST is used to initiate a conversion. Internal Clock The A/D converter has an internal clock that eliminates the need of synchronization between the external clock and the CS and RD signals found in other ADCs. The internal clock is factory trimmed to achieve a typical conversion time of 0.70s and a maximum conversion time over the full operating temperature range of 0.75s. No external adjustments are required. The guaranteed maximum acquisition time is 150ns. In addition, a throughput time of 800ns and a minimum sampling rate of 1.25Msps are guaranteed. Power Shutdown The LTC1415 provides two power shutdown modes, Nap and Sleep, to save power during inactive periods. The
Nap mode reduces the power by 87% and leaves only the digital logic and reference powered up. The wake-up time from Nap to active is 200ns. Follow the setup time shown in Figure 14a to avoid inadvertently invoking Sleep mode. In Sleep mode all bias currents are shut down and only leakage current remains, about 1A. Wake-up time from Sleep mode is much slower since the reference circuit must power up and settle to 0.01% for full 12-bit accuracy. Sleep mode wake-up time is dependent on the value of the capacitor connected to the REFCOMP (Pin 4). The wake-up time is 10ms with the recommended 10F capacitor. Shutdown is controlled by Pin 21 (SHDN); the ADC is in shutdown when it is low. The shutdown mode is selected with Pin 20 (NAP/SLP); high selects Nap.
NAP/SLP t3 SHDN
1415 F14a
Figure 14a. NAP/SLP to SHDN Timing
18
LTC1415
APPLICATI
SHDN
S I FOR ATIO
t4
CONVST
1415 F14b
Figure 14b. SHDN to CONVST Wake-Up Timing
Timing and Control Conversion start and data read operations are controlled by three digital inputs: CONVST, CS and RD. A logic "0" applied to the CONVST pin will start a conversion after the ADC has been selected (i.e., CS is low). Once initiated, it cannot be restarted until the conversion is complete. Converter status is indicated by the BUSY output. BUSY is low during a conversion. Figures 16 through 20 show several different modes of operation. In modes 1a and 1b (Figures 16 and 18) CS and RD are both tied low. The falling edge of CONVST starts the conversion. The data outputs are always enabled and data can be latched with the BUSY rising edge. Mode 1a shows operation with a narrow logic low CONVST pulse. Mode 1b shows a narrow logic high CONVST pulse. In mode 2 (Figure 18) CS is tied low. The falling edge of the CONVST signal again starts the conversion. Data outputs are in three-state until read by the MPU with the RD signal. Mode 2 can be used for operation with a shared MPU databus.
t CONV t5 CONVST t6 BUSY t7 DATA DATA (N - 1) DB11 TO DB0 DATA N DB11 TO DB0 DATA (N + 1) DB11 TO DB0
1415 * F16
Figure 16. Mode 1a CONVST Starts a Conversion. Data Outputs Always Enabled
U
In slow memory and ROM modes (Figures 19 and 20) CS is tied low and CONVST and RD are tied together. The MPU starts the conversion and reads the output with the RD signal. Conversions are started by the MPU or DSP (no external sample clock). In slow memory mode the processor applies a logic low to RD (= CONVST), starting the conversion. BUSY goes low, forcing the processor into a WAIT state. The previous conversion result appears on the data outputs. When the conversion is complete, the new conversion results appear on the data outputs; BUSY goes high, releasing the processor and the processor takes RD (= CONVST) back high and reads the new conversion data. In ROM mode, the processor takes RD (= CONVST) low, starting a conversion and reading the previous conversion result. After the conversion is complete, the processor can read the new result and initiate another conversion.
CS t2 CONVST t1 RD
1415 * F15
W
U
UO
Figure 15. CS to CONVST Setup Timing
t8
19
LTC1415
APPLICATI
S I FOR ATIO
tCONV t13 CONVST t6 BUSY t7 DATA DATA (N - 1) DB11 TO DB0 t6 t5
Figure 17. Mode 1b CONVST Starts a Conversion. Data is Read by RD
tCONV t5 CONVST t6 BUSY t9
RD t 10 DATA DATA N DB11 TO DB0
1415 F18
Figure 18. Mode 2 CONVST Starts a Conversion. Data is Read by RD
20
U
t8 t6 DATA N DB11 TO DB0 DATA (N + 1) DB11 TO DB0
1415 * F17
W
U
UO
t13 t8
t 11 t 12
LTC1415
APPLICATI
S I FOR ATIO
t CONV RD = CONVST t6 BUSY t 10 DATA DATA (N - 1) DB11 TO DB0 t7 DATA N DB11 TO DB0
Figure 19. Slow Memory Mode Timing
CS = 0 RD = CONVST t6 BUSY t 10 DATA
t CONV
t 11
DATA (N - 1) DB11 TO DB0
Figure 20. ROM Mode Timing
U
t8 t 11 DATA N DB11 TO DB0 DATA (N + 1) DB11-DB0
1415 * F19
W
U
UO
t8
DATA N DB11 TO DB0
1415 * F20
21
LTC1415
PACKAGE DESCRIPTIO U
Dimensions in inches (millimeters) unless otherwise noted.
G Package 28-Lead Plastic SSOP (0.209)
(LTC DWG # 05-08-1640)
0.397 - 0.407* (10.07 - 10.33) 28 27 26 25 24 23 22 21 20 19 18 17 16 15
0.301 - 0.311 (7.65 - 7.90)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 0.205 - 0.212** (5.20 - 5.38) 0.068 - 0.078 (1.73 - 1.99)
0 - 8
0.005 - 0.009 (0.13 - 0.22)
0.022 - 0.037 (0.55 - 0.95)
0.0256 (0.65) BSC
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
0.010 - 0.015 (0.25 - 0.38)
0.002 - 0.008 (0.05 - 0.21)
G28 SSOP 0694
22
LTC1415
PACKAGE DESCRIPTIO U
Dimensions in inches (millimeters) unless otherwise noted.
SW Package 28-Lead Plastic Small Outline (Wide 0.300)
(LTC DWG # 05-08-1620)
0.697 - 0.712* (17.70 - 18.08) 28 27 26 25 24 23 22 21 20 19 18 17 16 15
NOTE 1
0.394 - 0.419 (10.007 - 10.643)
0.291 - 0.299** (7.391 - 7.595) 0.010 - 0.029 x 45 (0.254 - 0.737) 0 - 8 TYP
1 0.093 - 0.104 (2.362 - 2.642)
2
3
4
5
6
7
8
9
10
11
12
13
14 0.037 - 0.045 (0.940 - 1.143)
0.009 - 0.013 (0.229 - 0.330)
NOTE 1 0.016 - 0.050 (0.406 - 1.270)
0.050 (1.270) TYP
NOTE: 1. PIN 1 IDENT, NOTCH ON TOP AND CAVITIES ON THE BOTTOM OF PACKAGES ARE THE MANUFACTURING OPTIONS. THE PART MAY BE SUPPLIED WITH OR WITHOUT ANY OF THE OPTIONS *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
0.014 - 0.019 (0.356 - 0.482) TYP
0.004 - 0.012 (0.102 - 0.305)
S28 (WIDE) 0996
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
23
LTC1415 RELATED PARTS
PART NUMBER LTC1273/75/76 LTC1274/77 LTC1278/79 LTC1282 LTC1409 LTC1410 LTC1419 LTC1605 DESCRIPTION Complete 5V Sampling 12-Bit ADCs with 70dB SINAD at Nyquist Low Power 12-Bit ADCs with Nap and Sleep Mode Shutdown High Speed Sampling 12-Bit ADCs with Shutdown Complete 3V 12-Bit ADC with 12mW Power Dissipation Low Power 12-Bit, 800ksps Sampling ADC 12-Bit, 1.25Msps Sampling ADC with Shutdown 14-Bit, 800ksps Sampling ADC 16-Bit, 100ksps Sampling ADC COMMENTS Lower Power 75mW and Cost Effective for fSAMPLE 300ksps Lowest Power (10mW) for fSAMPLE 100ksps Cost Effective 12-Bit ADCs with Convert Start Input Best for 300ksps < fSAMPLE 600ksps Fully Specified for 3V-Powered Applications, fSAMPLE 140ksps Best Dynamic Performance, fSAMPLE 800ksps, 80mW Dissipation Best Dynamic Performance, THD = 84 and SINAD = 71 at Nyquist 81.5dB SINAD, 150mW from 5V Supplies Single Supply, 10V Input Range, Low Power
24
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417 q (408) 432-1900 FAX: (408) 434-0507q TELEX: 499-3977 q www.linear-tech.com
1415f LT/TP 0497 7K * PRINTED IN USA
(c) LINEAR TECHNOLOGY CORPORATION 1996

▲Up To Search▲

Price & Availability of LTC1415

	To Download LTC1415 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .